An Efficient CPU Architecture for DSP Processors
نویسندگان
چکیده
Design narrative of an efficient CPU architecture dedicated to UTS-DSP (University of Tehran and Iran Communication Industries(SAMA) DSP) [1]-[10] is reported. Time and area consuming, the CPU architecture is a critical component of the overall architecture, which is responsible for execution of arithmetic and logical operations. The goal is composing an optimized hardware appropriate for executing the considered instruction set. To accomplish this goal, the required architecture has been modeled, verified and synthesized using VHDL description and synthesis tools.
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